1. Field of the Invention
The present invention relates to the management of a DRAM.
2. Discussion of the Related Art
It is generally known that, when a memory with a very fast access is desired, an SRAM is used. However, such a memory takes up a relatively large surface area since from 6 to 8 transistors are necessary to form an elementary memory cell.
Conversely, DRAMs have surface areas that can be much smaller, each elementary cell essentially including one transistor and one capacitive element.
However, it is often desired to form a memory having both the small surface area of a DRAM and the fast access features of an SRAM. It is for example desired to form a 144-Mbit single-chip memory with a possibility of access at each cycle of a clock having a 6.4-ns period (frequency on the order of 150 MHz).
The basic limitation of a DRAM is that the read or write access time of such a memory takes up several clock cycles, typically four clock cycles. This, essentially to take into account phases of preloading before each reading or writing of data and of rewriting after each reading of data, as well as to take into account relatively long switching times of the sense amplifiers of such a memory due to the low available signal level.
The general diagram of a system using a DRAM via a memory controller is very schematically illustrated in FIG. 1.
A DRAM 10 includes a great number of elementary blocks 11 and must be associated with read and write decoders (not shown). When a user (or a user program) desires access to memory 10, it must provide at least four indications:
a R/W indication indicating that it desires to read from or write into the memory,
an address indication @ to indicate to which memory cell it desires access,
an indication Data_in or D_in of the data that it desires to write (when it requires access in write mode), and
a request signal REQ to validate the access order.
When the memory access is an access in the read mode, data will be provided over an output bus Data_out or D_out.
Further, the memory must be periodically refreshed and receives a refresh control signal RF.
Indications R/W, @, REQ, and D_in are provided to a control block 12, which transmits the data to be written and which turns the input data essentially into data enabling access to a row (RAS or Row Access Strobe), data enabling access to a column (CAS or Column Access Strobe), row address data (@R), and column address data (@C).
Further, the memory must be periodically refreshed and receives a refresh control signal RF.
In fact, a row addressing is first performed, which operation takes some time. Then, once on a given row, it is possible to have access at the clock rate to various elements in the same row. This property is often used to enable fast access to DRAMs by properly gathering the input data according to the expected outputs, so that these data are preferentially successively located on a same line (so that the searched words are on a same page).
The case where the positions of the data to which access is successively desired are fully random and in which it is not possible to previously gather these data in a same page is here considered. Such is the case, for example, in communication applications on fast communication networks such as the Internet.